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See DataPath

MIPS 5 stage pipeline

1. Fetch instruction from memory
2. Read registers while decoding the instruction (the format of MIPS instructions allow reading and decoding to occur simultaneously)
3. Execute the operation or calculate an address
4. Access an operand in data memory.
5. Write the result into a register.

Structure Hazards

This means that the hardware can not support the combination of instructions that we want to execute in the same clock cycle. Since MIPS was designed with pipelining in mind it is fairly easy to avoid structural hazards. If we allowed instruction 1 & 4 simultaneously without providing two mechanisms to access memeory this could be a structural hazard.

Control Hazards

Control hazards arise from the need to make a decision (branch) before continuing. There are two solutions:

1. Stall: Just operate sequentially until the decision can be made. This is often refered to as inserting a bubble into the pipeline.
2. Predict: Make a guess and continue. If you are right nothing is lost, if you are wrong you have to start over just like a stall.

Prediction is obviously a better route! Dynamic branch prediction is about 90% accurate. Longer pipelines incur a larger penalty on a missed branch prediction! (P444 Computer Organization and Design)

Data Hazards

Suppose we have

     add $s0, $t0, $t1
     sub $t2, $s0, $t3

In this cas $s0 is accessed before it is written to the register!

     IF | ID/REG | ALU                         | (DA) | Reg |
                 | Value available from ALU                   Value available in Register
                                             \
                                              \  Forwarding
                                               \
                                                \   
        | IF     | ID/REG Needed               | ALU  | DA  | REG

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