|
Size: 182
Comment:
|
Size: 1894
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 9: | Line 9: |
= Ph.D. Qualifier Exams = == Building a Datapath == The datapath (or encoded logic) defines the path instructions and data follow through the hardware. It consists of '''State Elements''' which maintain the state, and '''Combinational Elements''' which operate on data. * Memory Unit holds and supplies instructions. '''State Element''' * Program Counter (PC) holds the address of the current instruction. '''State Element''' * ALU '''Combinational Elements''' * Registers '''State Elements''' * ... Instead of a single cycle datapath, we break the datapath into the following steps of the classic five stage pipeline: ||<#008080>Step name||<#008080>Action for R-type Instructions||<#008080>Action for memory-reference instructions||<#008080>Action for branches||<#008080>Action for jumps|| ||Instruction fetch||||||IR=Memroy[PC], PC=PC+4|| ||Instruction decode / register fetch |||||| A=Reg[IR[25-21]] / B=Reg[IR[20-16]] / ALUOut=PC+(sign-extended(IR[15-0])<< 2) || ||Execution, address computer, Branch jump completion || ALUOut=A op B || ALUOut=A+sign-extended(IR[15-0]) || if(A==B) then PC=ALUOut || PC=PC[31-28] | | (IR[25-0] << 2) || ||Memory access of R-type completion || Reg[IR[15-11]]=ALUOut || Load: MDR =Memory[ALUOut] OR Store: Memory[ALUOut]=B || || || ||Memory read completion || || Load: Reg[IR[20-16]]=MDR|| || || * Instruction Fetch ('''IF''') * Instruction decode and register fetch step. ('''IC''') Here we read the registers because we can without doing any harm. * Execution, memory address computation, or branch completion. ('''E''') * Memory access or R-type instruction completion step. ('''MA''') * Memory Read completion step. ('''MR''') |
Dissertation
Ph.D. Comprehensive Exam
= Ph.D. Qualifier Exams =
Building a Datapath
The datapath (or encoded logic) defines the path instructions and data follow through the hardware. It consists of State Elements which maintain the state, and Combinational Elements which operate on data.
Memory Unit holds and supplies instructions. State Element
Program Counter (PC) holds the address of the current instruction. State Element
ALU Combinational Elements
Registers State Elements
- ...
Instead of a single cycle datapath, we break the datapath into the following steps of the classic five stage pipeline:
Step name |
Action for R-type Instructions |
Action for memory-reference instructions |
Action for branches |
Action for jumps |
Instruction fetch |
IR=Memroy[PC], PC=PC+4 |
|||
Instruction decode / register fetch |
A=Reg[IR[25-21]] / B=Reg[IR[20-16]] / ALUOut=PC+(sign-extended(IR[15-0])<< 2) |
|||
Execution, address computer, Branch jump completion |
ALUOut=A op B |
ALUOut=A+sign-extended(IR[15-0]) |
if(A==B) then PC=ALUOut |
PC=PC[31-28] | | (IR[25-0] << 2) |
Memory access of R-type completion |
Reg[IR[15-11]]=ALUOut |
Load: MDR =Memory[ALUOut] OR Store: Memory[ALUOut]=B |
|
|
Memory read completion |
|
Load: Reg[IR[20-16]]=MDR |
|
|
Instruction Fetch (IF)
Instruction decode and register fetch step. (IC) Here we read the registers because we can without doing any harm.
Execution, memory address computation, or branch completion. (E)
Memory access or R-type instruction completion step. (MA)
Memory Read completion step. (MR)