2377
Comment:
|
2744
missing edit-log entry for this revision
|
Deletions are marked like this. | Additions are marked like this. |
Line 11: | Line 11: |
* CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
Line 14: | Line 18: |
* CriticalSection | |
Line 17: | Line 22: |
* DelayBandwidthProduct * DelayedBranch |
|
Line 19: | Line 26: |
* DelayBandwidthProduct * DelayedBranch |
|
Line 23: | Line 28: |
* DynamicSetOperations | |
Line 24: | Line 30: |
* ExpectedValue * FileSystem (Free BSD) |
|
Line 33: | Line 41: |
* GraphTheoryPage | |
Line 38: | Line 47: |
* InformationRetrieval | |
Line 44: | Line 54: |
* InvertedFile | |
Line 52: | Line 63: |
* MemoryHierarchy * MemoryStallClockCycles |
|
Line 58: | Line 71: |
* PageTable | |
Line 60: | Line 74: |
* PostingsFile | |
Line 65: | Line 80: |
* RaceCondition | |
Line 81: | Line 97: |
* ["taxonomy"] | |
Line 85: | Line 102: |
* ["taxonomy"] | * TreeStructures |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula