|
Size: 2202
Comment:
|
Size: 2584
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 10: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheLine |
|
| Line 13: | Line 17: |
| * CriticalSection | |
| Line 14: | Line 19: |
| * DataPath | |
| Line 15: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 17: | Line 25: |
| * DelayBandwidthProduct | |
| Line 21: | Line 28: |
| * ExpectedValue | |
| Line 25: | Line 33: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 34: | Line 43: |
| * InformationRetrievalSystem | |
| Line 41: | Line 51: |
| * LogicalMemory | |
| Line 47: | Line 58: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 53: | Line 66: |
| * PageTable | |
| Line 54: | Line 68: |
| * PipeLine | |
| Line 59: | Line 74: |
| * RaceCondition | |
| Line 73: | Line 89: |
| * SuperScalar | |
| Line 82: | Line 99: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula