2184
Comment:
|
2722
|
Deletions are marked like this. | Additions are marked like this. |
Line 10: | Line 10: |
* BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
Line 13: | Line 18: |
* CriticalSection | |
Line 14: | Line 20: |
* DataPath | |
Line 15: | Line 22: |
* DelayBandwidthProduct * DelayedBranch |
|
Line 17: | Line 26: |
* DelayBandwidthProduct | |
Line 20: | Line 28: |
* DynamicSetOperations | |
Line 21: | Line 30: |
* ExpectedValue * FileSystem (Free BSD) |
|
Line 25: | Line 36: |
* FloatingPointRepresentation (IEEE 754) | |
Line 34: | Line 46: |
* InformationRetrieval | |
Line 40: | Line 53: |
* InvertedFile | |
Line 41: | Line 55: |
* LogicalMemory | |
Line 44: | Line 59: |
* LinkerSteps | |
Line 46: | Line 62: |
* MemoryHierarchy * MemoryStallClockCycles |
|
Line 52: | Line 70: |
* PageTable | |
Line 53: | Line 72: |
* PipeLine * PostingsFile |
|
Line 58: | Line 79: |
* RaceCondition | |
Line 72: | Line 94: |
* SuperScalar | |
Line 73: | Line 96: |
* ["taxonomy"] | |
Line 77: | Line 101: |
* ["taxonomy"] | * TreeStructures |
Line 81: | Line 105: |
* VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula