|
Size: 2167
Comment:
|
Size: 2409
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 10: | Line 10: |
| * BoothsAlgorithm * ["Cache"] |
|
| Line 14: | Line 16: |
| * DataPath | |
| Line 15: | Line 18: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 17: | Line 22: |
| * DelayBandwidthProduct | |
| Line 25: | Line 29: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 41: | Line 46: |
| * LogicalMemory | |
| Line 44: | Line 50: |
| * LinkerSteps | |
| Line 49: | Line 56: |
| * ObjectFile | |
| Line 51: | Line 59: |
| * PageTable | |
| Line 52: | Line 61: |
| * PipeLine | |
| Line 71: | Line 81: |
| * SuperScalar | |
| Line 80: | Line 91: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
- ["Cache"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula