|
Size: 2046
Comment:
|
Size: 2337
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes | |
| Line 9: | Line 10: |
| * BoothsAlgorithm | |
| Line 12: | Line 14: |
| * CyclesPerInstruction (CPI) * DataPath |
|
| Line 16: | Line 20: |
| * DelayedBranch | |
| Line 23: | Line 28: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 30: | Line 36: |
| * HardwareDesignPrinciples | |
| Line 41: | Line 48: |
| * LinkerSteps | |
| Line 46: | Line 54: |
| * ObjectFile | |
| Line 49: | Line 58: |
| * PipeLine | |
| Line 55: | Line 65: |
| * ["Register"] (MIPS register) | |
| Line 67: | Line 78: |
| * SuperScalar |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula