|
Size: 2046
Comment:
|
Size: 2890
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes | |
| Line 9: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 12: | Line 18: |
| * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 13: | Line 22: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 15: | Line 26: |
| * DelayBandwidthProduct | |
| Line 18: | Line 28: |
| * DynamicSetOperations | |
| Line 19: | Line 30: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 21: | Line 34: |
| * FirstOrderTheory | |
| Line 23: | Line 37: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 27: | Line 42: |
| * GraphTheoryPage | |
| Line 30: | Line 46: |
| * HardwareDesignPrinciples | |
| Line 31: | Line 48: |
| * InformationRetrieval | |
| Line 37: | Line 55: |
| * InvertedFile | |
| Line 38: | Line 57: |
| * LogicalMemory | |
| Line 40: | Line 60: |
| * LeastFixedPoint | |
| Line 41: | Line 62: |
| * LinkerSteps | |
| Line 43: | Line 65: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 46: | Line 70: |
| * ObjectFile | |
| Line 48: | Line 73: |
| * PageTable | |
| Line 49: | Line 75: |
| * PipeLine * PostingsFile |
|
| Line 50: | Line 78: |
| * PresburgerArithmetic | |
| Line 54: | Line 83: |
| * RaceCondition | |
| Line 55: | Line 85: |
| * ["Register"] (MIPS register) | |
| Line 62: | Line 93: |
| * SemiAlgebraicSets | |
| Line 63: | Line 95: |
| * SemiLinearSets | |
| Line 67: | Line 100: |
| * SuperScalar | |
| Line 68: | Line 102: |
| * ["taxonomy"] | |
| Line 72: | Line 107: |
| * ["taxonomy"] | * TreeStructures |
| Line 75: | Line 110: |
| * UninterpretedFunctions | |
| Line 76: | Line 112: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula