Diff for "ComputerTerms"

Differences between revisions 81 and 113 (spanning 32 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheCoherenceProtocols
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FileSystem (Free BSD)
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrievalSystem
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
InvertedFile
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PostingsFile
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 81 as of 2004-02-16 20:53:14 → 
  Size: 1985
  Editor: velociraptor
  Comment:
+   ← Revision 113 as of 2004-04-02 01:15:46 → ⇥
  Size: 2680
  Editor: anonymous
  Comment: missing edit-log entry for this revision
-Deletions are marked like this.
+Additions are marked like this.
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+   * AddressingModes
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+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheCoherenceProtocols
   * CacheLine
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+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+   * DelayBandwidthProduct
   * DelayedBranch
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-   * DelayBandwidthProduct
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+Line 29:
+   * ExpectedValue
   * FileSystem (Free BSD)
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+   * FiveClassicPartsOfaComputer
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+Line 35:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 43:
+   * HardwareDesignPrinciples
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+   * InformationRetrievalSystem
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+Line 52:
+   * InvertedFile
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+Line 54:
+   * LogicalMemory
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+Line 58:
+   * LinkerSteps
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+Line 61:
+   * MemoryHierarchy
   * MemoryStallClockCycles
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+Line 66:
+   * ObjectFile
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+Line 69:
+   * PageTable
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+Line 71:
+   * PipeLine
   * PostingsFile
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+   * ["Processor"] or CPU
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+   * RaceCondition
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+   * ["Register"] (MIPS register)
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+   * SuperScalar
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+   * VirtualMemory