Diff for "ComputerTerms"

Differences between revisions 80 and 116 (spanning 36 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheCoherenceProtocols
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FileSystem (Free BSD)
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrieval
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
InvertedFile
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PostingsFile
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
["taxonomy"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
TreeStructures
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 80 as of 2004-02-16 20:16:42 → 
  Size: 1946
  Editor: velociraptor
  Comment:
+   ← Revision 116 as of 2004-08-13 19:03:59 → ⇥
  Size: 2695
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheCoherenceProtocols
   * CacheLine
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+Line 18:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 22:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 26:
-   * DelayBandwidthProduct
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+Line 29:
+   * ExpectedValue
   * FileSystem (Free BSD)
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+Line 33:
+   * FiveClassicPartsOfaComputer
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+Line 35:
+   * FloatingPointRepresentation (IEEE 754)
-Line 29:
+Line 43:
+   * HardwareDesignPrinciples
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+Line 45:
+   * InformationRetrieval
-Line 35:
+Line 51:
+   * InstructionSetArchitecture (ISA)
   * InvertedFile
-Line 36:
+Line 54:
+   * LogicalMemory
-Line 39:
+Line 58:
+   * LinkerSteps
-Line 41:
+Line 61:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 44:
+Line 66:
+   * ObjectFile
-Line 46:
+Line 69:
+   * PageTable
-Line 47:
+Line 71:
+   * PipeLine
   * PostingsFile
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+Line 76:
+   * ["Processor"] or CPU
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+Line 78:
+   * RaceCondition
-Line 52:
+Line 80:
+   * ["Register"] (MIPS register)
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+Line 93:
+   * SuperScalar
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+Line 95:
+   * ["taxonomy"]
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+Line 100:
-   * ["taxonomy"]
+   * TreeStructures
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+Line 104:
+   * VirtualMemory