Diff for "ComputerTerms"

Differences between revisions 80 and 109 (spanning 29 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrievalSystem
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 80 as of 2004-02-16 20:16:42 → 
  Size: 1946
  Editor: velociraptor
  Comment:
+   ← Revision 109 as of 2004-03-23 19:02:51 → ⇥
  Size: 2584
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
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+Line 17:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 21:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 25:
-   * DelayBandwidthProduct
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+Line 28:
+   * ExpectedValue
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+Line 31:
+   * FiveClassicPartsOfaComputer
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+Line 33:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 41:
+   * HardwareDesignPrinciples
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+Line 43:
+   * InformationRetrievalSystem
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+Line 49:
+   * InstructionSetArchitecture (ISA)
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+Line 51:
+   * LogicalMemory
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+Line 55:
+   * LinkerSteps
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+Line 58:
+   * MemoryHierarchy
   * MemoryStallClockCycles
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+Line 63:
+   * ObjectFile
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+Line 66:
+   * PageTable
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+Line 68:
+   * PipeLine
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+Line 72:
+   * ["Processor"] or CPU
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+Line 74:
+   * RaceCondition
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+   * ["Register"] (MIPS register)
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+   * SuperScalar
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+   * VirtualMemory