|
Size: 1946
Comment:
|
Size: 2454
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes | |
| Line 9: | Line 10: |
| * BoothsAlgorithm * CaChe |
|
| Line 12: | Line 15: |
| * CyclesPerInstruction (CPI) * DataPath |
|
| Line 13: | Line 18: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 15: | Line 22: |
| * DelayBandwidthProduct | |
| Line 21: | Line 27: |
| * FiveClassicPartsOfaComputer | |
| Line 22: | Line 29: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 29: | Line 37: |
| * HardwareDesignPrinciples | |
| Line 35: | Line 44: |
| * InstructionSetArchitecture (ISA) | |
| Line 36: | Line 46: |
| * LogicalMemory | |
| Line 39: | Line 50: |
| * LinkerSteps | |
| Line 41: | Line 53: |
| * MemoryStallClockCycles | |
| Line 44: | Line 57: |
| * ObjectFile | |
| Line 46: | Line 60: |
| * PageTable | |
| Line 47: | Line 62: |
| * PipeLine | |
| Line 50: | Line 66: |
| * ["Processor"] or CPU | |
| Line 51: | Line 68: |
| * RaceCondition | |
| Line 52: | Line 70: |
| * ["Register"] (MIPS register) | |
| Line 64: | Line 83: |
| * SuperScalar | |
| Line 73: | Line 93: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula