Diff for "ComputerTerms"

Differences between revisions 79 and 115 (spanning 36 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheCoherenceProtocols
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FileSystem (Free BSD)
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrieval
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
InvertedFile
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PostingsFile
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 79 as of 2004-02-11 15:35:50 → 
  Size: 1928
  Editor: pcp015622pcs
  Comment:
+   ← Revision 115 as of 2004-04-08 15:17:59 → ⇥
  Size: 2674
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheCoherenceProtocols
   * CacheLine
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+Line 18:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 22:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 26:
-   * DelayBandwidthProduct
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+Line 29:
+   * ExpectedValue
   * FileSystem (Free BSD)
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+Line 33:
+   * FiveClassicPartsOfaComputer
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+Line 35:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 37:
+   * FrameBuffer
-Line 28:
+Line 43:
+   * HardwareDesignPrinciples
-Line 29:
+Line 45:
+   * InformationRetrieval
-Line 34:
+Line 51:
+   * InstructionSetArchitecture (ISA)
   * InvertedFile
-Line 35:
+Line 54:
+   * LogicalMemory
-Line 38:
+Line 58:
+   * LinkerSteps
-Line 40:
+Line 61:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 43:
+Line 66:
+   * ObjectFile
-Line 45:
+Line 69:
+   * PageTable
-Line 46:
+Line 71:
+   * PipeLine
   * PostingsFile
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+Line 76:
+   * ["Processor"] or CPU
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+Line 78:
+   * RaceCondition
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+Line 80:
+   * ["Register"] (MIPS register)
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+Line 93:
+   * SuperScalar
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+Line 103:
+   * VirtualMemory