Diff for "ComputerTerms"

Differences between revisions 78 and 112 (spanning 34 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FileSystem (Free BSD)
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrievalSystem
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
InvertedFile
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PostingsFile
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 78 as of 2004-01-25 18:17:35 → 
  Size: 1910
  Editor: yakko
  Comment:
+   ← Revision 112 as of 2004-03-31 17:21:34 → ⇥
  Size: 2650
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
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+Line 17:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 21:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 25:
-   * DelayBandwidthProduct
-Line 19:
+Line 28:
+   * ExpectedValue
   * FileSystem (Free BSD)
-Line 21:
+Line 32:
+   * FiveClassicPartsOfaComputer
-Line 22:
+Line 34:
+   * FloatingPointRepresentation (IEEE 754)
-Line 23:
+Line 36:
+   * FrameBuffer
-Line 27:
+Line 41:
+   * HammingCode
   * HardwareDesignPrinciples
-Line 28:
+Line 44:
+   * InformationRetrievalSystem
-Line 33:
+Line 50:
+   * InstructionSetArchitecture (ISA)
   * InvertedFile
-Line 34:
+Line 53:
+   * LogicalMemory
-Line 37:
+Line 57:
+   * LinkerSteps
-Line 39:
+Line 60:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 42:
+Line 65:
+   * ObjectFile
-Line 44:
+Line 68:
+   * PageTable
-Line 45:
+Line 70:
+   * PipeLine
   * PostingsFile
-Line 48:
+Line 75:
+   * ["Processor"] or CPU
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+Line 77:
+   * RaceCondition
-Line 50:
+Line 79:
+   * ["Register"] (MIPS register)
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+Line 92:
+   * SuperScalar
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+Line 102:
+   * VirtualMemory