|
Size: 1893
Comment:
|
Size: 2393
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 8: | Line 10: |
| * BoothsAlgorithm | |
| Line 11: | Line 14: |
| * CyclesPerInstruction (CPI) * DataPath |
|
| Line 12: | Line 17: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 14: | Line 21: |
| * DelayBandwidthProduct | |
| Line 20: | Line 26: |
| * FiveClassicPartsOfaComputer | |
| Line 21: | Line 28: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 22: | Line 30: |
| * FrameBuffer | |
| Line 26: | Line 35: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 32: | Line 43: |
| * InstructionSetArchitecture (ISA) | |
| Line 33: | Line 45: |
| * LogicalMemory | |
| Line 36: | Line 49: |
| * LinkerSteps | |
| Line 41: | Line 55: |
| * ObjectFile | |
| Line 43: | Line 58: |
| * PageTable | |
| Line 44: | Line 60: |
| * PipeLine | |
| Line 47: | Line 64: |
| * ["Processor"] or CPU | |
| Line 49: | Line 67: |
| * ["Register"] (MIPS register) | |
| Line 61: | Line 80: |
| * SuperScalar | |
| Line 70: | Line 90: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula