Diff for "ComputerTerms"

Differences between revisions 77 and 110 (spanning 33 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrievalSystem
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
InvertedFile
PostingFile
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 77 as of 2004-01-25 17:52:43 → 
  Size: 1893
  Editor: yakko
  Comment:
+   ← Revision 110 as of 2004-03-26 21:14:50 → ⇥
  Size: 2621
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
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+Line 17:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
-Line 12:
+Line 21:
+   * DelayBandwidthProduct
   * DelayedBranch
-Line 14:
+Line 25:
-   * DelayBandwidthProduct
-Line 18:
+Line 28:
+   * ExpectedValue
-Line 20:
+Line 31:
+   * FiveClassicPartsOfaComputer
-Line 21:
+Line 33:
+   * FloatingPointRepresentation (IEEE 754)
-Line 22:
+Line 35:
+   * FrameBuffer
-Line 26:
+Line 40:
+   * HammingCode
   * HardwareDesignPrinciples
-Line 27:
+Line 43:
+   * InformationRetrievalSystem
-Line 32:
+Line 49:
+   * InstructionSetArchitecture (ISA)
   * InvertedFile
   * PostingFile
-Line 33:
+Line 53:
+   * LogicalMemory
-Line 36:
+Line 57:
+   * LinkerSteps
-Line 38:
+Line 60:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 41:
+Line 65:
+   * ObjectFile
-Line 43:
+Line 68:
+   * PageTable
-Line 44:
+Line 70:
+   * PipeLine
-Line 47:
+Line 74:
+   * ["Processor"] or CPU
-Line 48:
+Line 76:
+   * RaceCondition
-Line 49:
+Line 78:
+   * ["Register"] (MIPS register)
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+Line 91:
+   * SuperScalar
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+Line 101:
+   * VirtualMemory