|
Size: 1836
Comment:
|
Size: 2680
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 10: | Line 18: |
| * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 11: | Line 22: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 13: | Line 26: |
| * DelayBandwidthProduct | |
| Line 17: | Line 29: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 19: | Line 33: |
| * FiveClassicPartsOfaComputer | |
| Line 20: | Line 35: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 21: | Line 37: |
| * FrameBuffer | |
| Line 22: | Line 39: |
| * GeometricMean | |
| Line 24: | Line 42: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 25: | Line 45: |
| * InformationRetrievalSystem | |
| Line 30: | Line 51: |
| * InstructionSetArchitecture (ISA) * InvertedFile |
|
| Line 31: | Line 54: |
| * LogicalMemory | |
| Line 34: | Line 58: |
| * LinkerSteps | |
| Line 36: | Line 61: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 39: | Line 66: |
| * ObjectFile | |
| Line 41: | Line 69: |
| * PageTable | |
| Line 42: | Line 71: |
| * PipeLine * PostingsFile |
|
| Line 45: | Line 76: |
| * ["Processor"] or CPU | |
| Line 46: | Line 78: |
| * RaceCondition | |
| Line 47: | Line 80: |
| * ["Register"] (MIPS register) | |
| Line 59: | Line 93: |
| * SuperScalar | |
| Line 68: | Line 103: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula