|
Size: 1802
Comment:
|
Size: 2650
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheLine |
|
| Line 9: | Line 16: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 10: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 12: | Line 25: |
| * DelayBandwidthProduct | |
| Line 16: | Line 28: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 18: | Line 32: |
| * FiveClassicPartsOfaComputer | |
| Line 19: | Line 34: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 20: | Line 36: |
| * FrameBuffer | |
| Line 21: | Line 38: |
| * GeometricMean | |
| Line 23: | Line 41: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 24: | Line 44: |
| * InformationRetrievalSystem | |
| Line 29: | Line 50: |
| * InstructionSetArchitecture (ISA) * InvertedFile |
|
| Line 30: | Line 53: |
| * LogicalMemory | |
| Line 33: | Line 57: |
| * LinkerSteps | |
| Line 35: | Line 60: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 38: | Line 65: |
| * ObjectFile | |
| Line 40: | Line 68: |
| * PageTable | |
| Line 41: | Line 70: |
| * PipeLine * PostingsFile |
|
| Line 44: | Line 75: |
| * ["Processor"] or CPU | |
| Line 45: | Line 77: |
| * RaceCondition | |
| Line 46: | Line 79: |
| * ["Register"] (MIPS register) | |
| Line 58: | Line 92: |
| * SuperScalar | |
| Line 67: | Line 102: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula