Diff for "ComputerTerms"

Differences between revisions 72 and 106 (spanning 34 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 72 as of 2004-01-25 16:04:26 → 
  Size: 1784
  Editor: yakko
  Comment:
+   ← Revision 106 as of 2004-03-18 21:32:29 → ⇥
  Size: 2531
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
-Line 4:
+Line 6:
+   * AverageNormalizedExecutionTime
-Line 7:
+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
-Line 9:
+Line 16:
+   * CpuTime
   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
-Line 10:
+Line 21:
+   * DelayBandwidthProduct
   * DelayedBranch
-Line 12:
+Line 25:
-   * DelayBandwidthProduct
-Line 18:
+Line 30:
+   * FiveClassicPartsOfaComputer
-Line 19:
+Line 32:
+   * FloatingPointRepresentation (IEEE 754)
-Line 20:
+Line 34:
+   * FrameBuffer
-Line 21:
+Line 36:
+   * GeometricMean
-Line 23:
+Line 39:
+   * HammingCode
   * HardwareDesignPrinciples
-Line 29:
+Line 47:
+   * InstructionSetArchitecture (ISA)
-Line 30:
+Line 49:
+   * LogicalMemory
-Line 31:
+Line 51:
+   * ["Latency"]
-Line 32:
+Line 53:
+   * LinkerSteps
-Line 34:
+Line 56:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 37:
+Line 61:
+   * ObjectFile
-Line 39:
+Line 64:
+   * PageTable
-Line 40:
+Line 66:
+   * PipeLine
-Line 43:
+Line 70:
+   * ["Processor"] or CPU
-Line 44:
+Line 72:
+   * RaceCondition
-Line 45:
+Line 74:
+   * ["Register"] (MIPS register)
-Line 57:
+Line 87:
+   * SuperScalar
-Line 66:
+Line 97:
+   * VirtualMemory
   * WallClockTime