|
Size: 1767
Comment:
|
Size: 2744
Comment: missing edit-log entry for this revision
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 9: | Line 17: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 10: | Line 22: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 12: | Line 26: |
| * DelayBandwidthProduct | |
| Line 15: | Line 28: |
| * DynamicSetOperations | |
| Line 16: | Line 30: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 18: | Line 34: |
| * FiveClassicPartsOfaComputer | |
| Line 19: | Line 36: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 20: | Line 38: |
| * FrameBuffer | |
| Line 21: | Line 40: |
| * GeometricMean * GraphTheoryPage |
|
| Line 23: | Line 44: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 24: | Line 47: |
| * InformationRetrieval | |
| Line 29: | Line 53: |
| * InstructionSetArchitecture (ISA) * InvertedFile |
|
| Line 30: | Line 56: |
| * LogicalMemory | |
| Line 31: | Line 58: |
| * ["Latency"] | |
| Line 32: | Line 60: |
| * LinkerSteps | |
| Line 34: | Line 63: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 37: | Line 68: |
| * ObjectFile | |
| Line 39: | Line 71: |
| * PageTable | |
| Line 40: | Line 73: |
| * PipeLine * PostingsFile |
|
| Line 43: | Line 78: |
| * ["Processor"] or CPU | |
| Line 44: | Line 80: |
| * RaceCondition | |
| Line 45: | Line 82: |
| * ["Register"] (MIPS register) | |
| Line 57: | Line 95: |
| * SuperScalar | |
| Line 58: | Line 97: |
| * ["taxonomy"] | |
| Line 60: | Line 100: |
| * ThroughPut | |
| Line 61: | Line 102: |
| * ["taxonomy"] | * TreeStructures |
| Line 65: | Line 106: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula