Diff for "ComputerTerms"

Differences between revisions 65 and 104 (spanning 39 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 65 as of 2004-01-14 23:15:40 → 
  Size: 1735
  Editor: dot
  Comment:
+   ← Revision 104 as of 2004-03-17 19:48:20 → ⇥
  Size: 2476
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+   * AverageNormalizedExecutionTime
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
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+Line 14:
+   * CpuTime
   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 19:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 23:
-   * DelayBandwidthProduct
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+Line 25:
+   * ExecutionTime
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+Line 28:
+   * FiveClassicPartsOfaComputer
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+Line 30:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 32:
+   * FrameBuffer
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+Line 34:
+   * GeometricMean
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+Line 37:
+   * HammingCode
   * HardwareDesignPrinciples
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+Line 45:
+   * InstructionSetArchitecture (ISA)
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+Line 47:
+   * LogicalMemory
-Line 30:
+Line 49:
+   * ["Latency"]
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+Line 51:
+   * LinkerSteps
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+Line 54:
+   * MemoryStallClockCycles
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+Line 57:
-   * MultiProtocolLabelSwitching (MPLS)
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+Line 58:
+   * ObjectFile
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+Line 61:
+   * PageTable
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+Line 63:
+   * PipeLine
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+Line 67:
+   * ["Processor"] or CPU
   * QueuingTheory
   * RaceCondition
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+Line 71:
+   * ["Register"] (MIPS register)
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+Line 73:
+   * ResponseTime
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+Line 83:
+   * SpeedUp
   * SuperScalar
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+Line 88:
+   * ThroughPut
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+Line 94:
+   * VirtualMemory
   * WallClockTime