|
Size: 1713
Comment:
|
Size: 2269
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm | |
| Line 9: | Line 13: |
| * CpuTime * CyclesPerInstruction (CPI) |
|
| Line 15: | Line 21: |
| * ExecutionTime | |
| Line 17: | Line 24: |
| * FiveClassicPartsOfaComputer | |
| Line 18: | Line 26: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 19: | Line 28: |
| * FrameBuffer | |
| Line 20: | Line 30: |
| * GeometricMean | |
| Line 22: | Line 33: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 28: | Line 41: |
| * InstructionSetArchitecture (ISA) | |
| Line 30: | Line 44: |
| * ["Latency"] | |
| Line 31: | Line 46: |
| * LinkerSteps | |
| Line 35: | Line 51: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 37: | Line 52: |
| * ObjectFile | |
| Line 39: | Line 55: |
| * ["Performance"] | |
| Line 42: | Line 59: |
| * ["Processor"] or CPU * QueuingTheory |
|
| Line 43: | Line 62: |
| * ["Register"] (MIPS register) | |
| Line 44: | Line 64: |
| * ResponseTime | |
| Line 53: | Line 74: |
| * SpeedUp | |
| Line 56: | Line 78: |
| * ThroughPut | |
| Line 61: | Line 84: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula