Diff for "ComputerTerms"

Differences between revisions 63 and 91 (spanning 28 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
["Dichotomy"]
DijkstrasAlgorithm
DelayBandwidthProduct
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
["Performance"]
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
WallClockTime

-  ⇤ ← Revision 63 as of 2003-11-19 00:59:23 → 
  Size: 1639
  Editor: yakko
  Comment:
+   ← Revision 91 as of 2004-02-19 23:59:22 → ⇥
  Size: 2269
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+   * AverageNormalizedExecutionTime
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+   * BoothsAlgorithm
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+   * CpuTime
   * CyclesPerInstruction (CPI)
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+   * DelayBandwidthProduct
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+Line 21:
+   * ExecutionTime
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+Line 24:
+   * FiveClassicPartsOfaComputer
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+Line 26:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 28:
+   * FrameBuffer
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+Line 30:
+   * GeometricMean
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+Line 33:
+   * HammingCode
   * HardwareDesignPrinciples
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+Line 41:
+   * InstructionSetArchitecture (ISA)
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+Line 44:
+   * ["Latency"]
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+Line 46:
+   * LinkerSteps
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+Line 51:
-   * MultiProtocolLabelSwitching (MPLS)
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+Line 52:
+   * ObjectFile
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+Line 55:
+   * ["Performance"]
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+Line 59:
+   * ["Processor"] or CPU
   * QueuingTheory
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+Line 62:
+   * ["Register"] (MIPS register)
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+Line 64:
+   * ResponseTime
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+   * SpeedUp
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+Line 76:
+   * TcpFastRetransmit
   * TcpFastRecovery
   * ThroughPut
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+Line 84:
+   * WallClockTime