Diff for "ComputerTerms"

Differences between revisions 62 and 93 (spanning 31 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
["Dichotomy"]
DijkstrasAlgorithm
DelayBandwidthProduct
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
WallClockTime

-  ⇤ ← Revision 62 as of 2003-11-19 00:59:13 → 
  Size: 1640
  Editor: yakko
  Comment:
+   ← Revision 93 as of 2004-02-26 16:39:32 → ⇥
  Size: 2299
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+Line 6:
-   * ["Bijections"]
+   * AverageNormalizedExecutionTime
   * ["Bijection"]
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+Line 10:
+   * BoothsAlgorithm
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+Line 13:
+   * CpuTime
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 19:
+   * DelayBandwidthProduct
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+Line 22:
+   * ExecutionTime
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+Line 25:
+   * FiveClassicPartsOfaComputer
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+Line 27:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 29:
+   * FrameBuffer
-Line 19:
+Line 31:
+   * GeometricMean
-Line 21:
+Line 34:
+   * HammingCode
   * HardwareDesignPrinciples
-Line 27:
+Line 42:
+   * InstructionSetArchitecture (ISA)
-Line 29:
+Line 45:
+   * ["Latency"]
-Line 30:
+Line 47:
+   * LinkerSteps
-Line 34:
+Line 52:
-   * MultiProtocolLabelSwitching (MPLS)
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+Line 53:
+   * ObjectFile
-Line 38:
+Line 56:
+   * ["Performance"]
   * PipeLine
-Line 41:
+Line 61:
+   * ["Processor"] or CPU
   * QueuingTheory
-Line 42:
+Line 64:
+   * ["Register"] (MIPS register)
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+Line 66:
+   * ResponseTime
-Line 52:
+Line 76:
+   * SpeedUp
-Line 53:
+Line 78:
+   * TcpFastRetransmit
   * TcpFastRecovery
   * ThroughPut
-Line 58:
+Line 86:
+   * WallClockTime