Diff for "ComputerTerms"

Differences between revisions 61 and 102 (spanning 41 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 61 as of 2003-11-19 00:26:26 → 
  Size: 1619
  Editor: yakko
  Comment:
+   ← Revision 102 as of 2004-03-15 02:50:28 → ⇥
  Size: 2434
  Editor: dot
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+Line 6:
+   * AverageNormalizedExecutionTime
   * ["Bijection"]
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
-Line 8:
+Line 14:
+   * CpuTime
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 18:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 24:
+   * ExecutionTime
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+Line 27:
+   * FiveClassicPartsOfaComputer
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+Line 29:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 31:
+   * FrameBuffer
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+Line 33:
+   * GeometricMean
-Line 20:
+Line 36:
+   * HammingCode
   * HardwareDesignPrinciples
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+Line 44:
+   * InstructionSetArchitecture (ISA)
-Line 27:
+Line 46:
+   * LogicalMemory
-Line 28:
+Line 48:
+   * ["Latency"]
-Line 29:
+Line 50:
+   * LinkerSteps
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+Line 53:
+   * MemoryStallClockCycles
-Line 33:
+Line 56:
-   * MultiProtocolLabelSwitching (MPLS)
-Line 35:
+Line 57:
+   * ObjectFile
-Line 37:
+Line 60:
+   * PageTable
   * ["Performance"]
   * PipeLine
-Line 40:
+Line 66:
+   * ["Processor"] or CPU
   * QueuingTheory
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+Line 69:
+   * ["Register"] (MIPS register)
-Line 42:
+Line 71:
+   * ResponseTime
-Line 51:
+Line 81:
+   * SpeedUp
   * SuperScalar
-Line 52:
+Line 84:
+   * TcpFastRetransmit
   * TcpFastRecovery
   * ThroughPut
-Line 57:
+Line 92:
+   * VirtualMemory
   * WallClockTime