|
Size: 1553
Comment:
|
Size: 2202
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra |
|
| Line 7: | Line 12: |
| * CpuTime * CyclesPerInstruction (CPI) |
|
| Line 10: | Line 17: |
| * DelayBandwidthProduct | |
| Line 12: | Line 20: |
| * ExecutionTime | |
| Line 14: | Line 23: |
| * FiveClassicPartsOfaComputer | |
| Line 16: | Line 26: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean |
|
| Line 18: | Line 31: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 24: | Line 39: |
| * InstructionSetArchitecture (ISA) | |
| Line 26: | Line 42: |
| * ["Latency"] | |
| Line 27: | Line 44: |
| * LinkerSteps | |
| Line 31: | Line 49: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 33: | Line 50: |
| * ObjectFile | |
| Line 35: | Line 53: |
| * ["Performance"] | |
| Line 38: | Line 57: |
| * ["Processor"] or CPU * QueuingTheory |
|
| Line 39: | Line 60: |
| * ["Register"] (MIPS register) | |
| Line 40: | Line 62: |
| * ResponseTime | |
| Line 48: | Line 71: |
| * SpatialExtent * SpeedUp |
|
| Line 49: | Line 74: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
| Line 54: | Line 82: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula