Diff for "ComputerTerms"

Differences between revisions 58 and 105 (spanning 47 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 58 as of 2003-11-04 00:26:43 → 
  Size: 1553
  Editor: wakko
  Comment:
+   ← Revision 105 as of 2004-03-18 20:54:38 → ⇥
  Size: 2498
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+Line 6:
+   * AverageNormalizedExecutionTime
   * ["Bijection"]
   * BooleanAlgebra
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
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+Line 14:
+   * CpuTime
   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
-Line 8:
+Line 19:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 25:
+   * ExecutionTime
-Line 14:
+Line 28:
+   * FiveClassicPartsOfaComputer
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+Line 30:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 32:
+   * FrameBuffer
   * FreeBooleanAlgebra
   * GeometricMean
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+Line 37:
+   * HammingCode
   * HardwareDesignPrinciples
-Line 24:
+Line 45:
+   * InstructionSetArchitecture (ISA)
-Line 25:
+Line 47:
+   * LogicalMemory
-Line 26:
+Line 49:
+   * ["Latency"]
-Line 27:
+Line 51:
+   * LinkerSteps
-Line 29:
+Line 54:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 31:
+Line 58:
-   * MultiProtocolLabelSwitching (MPLS)
-Line 33:
+Line 59:
+   * ObjectFile
-Line 35:
+Line 62:
+   * PageTable
   * ["Performance"]
   * PipeLine
-Line 38:
+Line 68:
+   * ["Processor"] or CPU
   * QueuingTheory
   * RaceCondition
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+Line 72:
+   * ["Register"] (MIPS register)
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+Line 74:
+   * ResponseTime
-Line 48:
+Line 83:
+   * SpatialExtent
   * SpeedUp
   * SuperScalar
-Line 49:
+Line 87:
+   * TcpFastRetransmit
   * TcpFastRecovery
   * ThroughPut
-Line 54:
+Line 95:
+   * VirtualMemory
   * WallClockTime