|
Size: 1535
Comment:
|
Size: 2224
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm |
|
| Line 6: | Line 13: |
| * CpuTime * CyclesPerInstruction (CPI) |
|
| Line 9: | Line 18: |
| * DelayBandwidthProduct | |
| Line 11: | Line 21: |
| * ExecutionTime | |
| Line 13: | Line 24: |
| * FiveClassicPartsOfaComputer | |
| Line 15: | Line 27: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean |
|
| Line 17: | Line 32: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 23: | Line 40: |
| * InstructionSetArchitecture (ISA) | |
| Line 25: | Line 43: |
| * ["Latency"] | |
| Line 26: | Line 45: |
| * LinkerSteps | |
| Line 30: | Line 50: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 32: | Line 51: |
| * ObjectFile | |
| Line 34: | Line 54: |
| * ["Performance"] | |
| Line 37: | Line 58: |
| * ["Processor"] or CPU * QueuingTheory |
|
| Line 38: | Line 61: |
| * ["Register"] (MIPS register) | |
| Line 39: | Line 63: |
| * ResponseTime | |
| Line 47: | Line 72: |
| * SpatialExtent * SpeedUp |
|
| Line 48: | Line 75: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
| Line 53: | Line 83: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula