1535
Comment:
|
2079
|
Deletions are marked like this. | Additions are marked like this. |
Line 1: | Line 1: |
* AmdahlsLaw | |
Line 4: | Line 5: |
* AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm |
|
Line 6: | Line 11: |
* CpuTime * CyclesPerInstruction (CPI) |
|
Line 9: | Line 16: |
* DelayBandwidthProduct | |
Line 11: | Line 19: |
* ExecutionTime | |
Line 13: | Line 22: |
* FiveClassicPartsOfaComputer | |
Line 15: | Line 25: |
* FrameBuffer * FreeBooleanAlgebra * GeometricMean |
|
Line 17: | Line 30: |
* HammingCode | |
Line 23: | Line 37: |
* InstructionSetArchitecture (ISA) | |
Line 25: | Line 40: |
* ["Latency"] | |
Line 30: | Line 46: |
* MultiProtocolLabelSwitching (MPLS) | |
Line 34: | Line 49: |
* ["Performance"] | |
Line 37: | Line 53: |
* ["Processor"] or CPU * QueuingTheory |
|
Line 39: | Line 57: |
* ResponseTime | |
Line 47: | Line 66: |
* SpatialExtent * SpeedUp |
|
Line 48: | Line 69: |
* TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
Line 53: | Line 77: |
* WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula