|
Size: 711
Comment:
|
Size: 2531
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw * AreaBorderRouter |
|
| Line 2: | Line 5: |
| * AutonomousSystem (AS) * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm * CaChe * CacheBlock * CacheLine * CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions) |
|
| Line 3: | Line 16: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath * ["Decidable"] and SemiDecidable * DelayBandwidthProduct * DelayedBranch * ["Dichotomy"] |
|
| Line 4: | Line 25: |
| * DisjunctiveSyllogism | |
| Line 5: | Line 27: |
| * ExecutionTime | |
| Line 7: | Line 30: |
| * FiveClassicPartsOfaComputer * FixedPoint * FloatingPointRepresentation (IEEE 754) * ForwardingVsRouting * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GroundClause * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples * HypotheticalSylogism |
|
| Line 10: | Line 45: |
| * InternetProtocolV6 (IPv6) | |
| Line 11: | Line 47: |
| * InstructionSetArchitecture (ISA) * LogicalImplication (|= symbol and also |-) * LogicalMemory |
|
| Line 12: | Line 51: |
| * ["Latency"] | |
| Line 13: | Line 53: |
| * LinkerSteps | |
| Line 15: | Line 56: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 16: | Line 59: |
| * MultiProtocolLabelSwitching (MPLS) | * ModusPonens * MonotoneBooleanTerm * ObjectFile |
| Line 18: | Line 63: |
| * OsiModel (7 layer OSI network Model) * PageTable * ["Performance"] * PipeLine |
|
| Line 19: | Line 68: |
| * PowerSet * ["Proposition"] or PropositionalLogic * ["Processor"] or CPU * QueuingTheory * RaceCondition * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime * RoutingArea |
|
| Line 22: | Line 81: |
| * SemanticsSyntaxSortsInLogic * SemiDecidable and ["Decidable"] * SequenceNumber * SlidingWindowProtocol * SpatialExtent * SpeedUp * SuperScalar * ["Tautology"] * TcpFastRetransmit * TcpFastRecovery * ThroughPut * TransmissionControlProtocol (TCP) |
|
| Line 24: | Line 95: |
| * ["Undecidable"] | |
| Line 25: | Line 97: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula