|
Size: 2476
Comment:
|
Size: 2650
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 12: | Line 12: |
| * CacheBlock * CacheLine |
|
| Line 26: | Line 28: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 40: | Line 44: |
| * InformationRetrievalSystem | |
| Line 46: | Line 51: |
| * InvertedFile | |
| Line 54: | Line 60: |
| * MemoryHierarchy | |
| Line 64: | Line 71: |
| * PostingsFile |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula