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=== Cache Misses === A ''data cache miss'' requires us to "freeze" the processor on the instruction that caused the miss. We then retrieve the data from memory, place it in cache and restart the instruction - this time we are guaranteed a hit. |
Cache
Direct Mapped Cache
Cache's are directed mapped if each memory location is mapped to exactly one location in the cache. An example would be:
location = (Block Address) MOD (Number of cache blocks in the cache)
In this way we can map a memory location to a cache location.
Example: Suppose we have a cache with 8 slots 2^3. Then a word at 45 would be found at slot 5 in the cache.
https://www.scotnpatti.com/images/directmappedcache.jpg
Tags contain the address information required to identify if the information in a cache location coresponds to the data needed. These tags contain the upper bits of the memory address. NOTE: The byte offset is the number of bits required to specify bytes in a block. Since this example uses 4 byte (word) sized blocks the byte offset is 2 bits
https://www.scotnpatti.com/images/directmappedcache2.jpg
To determine the size of the cache above:
cache size = (number of locations=1024 = 2^10) X (Block size = 32 + Validity bit = 1 + (32 - TagSize=10 - Block bits = 2)
= 2^10 X (32 + 1 + 32 - 10 - 2)
= 1024 X (53)
= 54,272 bits or 6,784 bytesHow many bits are required for a direct-mapped cache with 64 KB of data and one-word blocks, assuming a 32-bit address.
64/4 = 16 KWords = 2^16 Cache Size = 2^16 X (32 + (32 - 16 - 2) + 1) = 2^16 X 49 = 802816 bits = 100,352 bytes = 98 KB.
Cache Misses
A data cache miss requires us to "freeze" the processor on the instruction that caused the miss. We then retrieve the data from memory, place it in cache and restart the instruction - this time we are guaranteed a hit.