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See: CaChe, VirtualMemory (includes: TLB, and Page table)

Pitfalls:

'''Don't forget to account for byte addressing or the cache block size in simulating a cache. '''

Example: If we have a 32-byte, direct-mapped cache with a block size of 4 bytes, the byte address 36 maps into block 1 of the cache since byte addres 36 is block address 9 and (9 mod 8)=1. On the other hand if address 36 is a word address, then it maps into block (36 mod 8)=6. NOTE: here the size of the cache in blocks is what counts: 32/4=8 blocks.

Example: Suppose we have a cache with 256 bytes and a block size of 32 bytes. Which block does the byte address 300 fall into? 
{{{
Byte address 300 is 

  Int(300/32) = 9

The number of blocks in the cace is Int(256/32) = 8

Block #9 falls into cache block number (9 mod 8) = 1
}}}

'''Using miss rate as teh only metric for evaluating a memory hierarchy'''

You should also include hit time. Recall

{{{
   CPU time = (CPU execution clock cycles + Mem-stall cycles) x ClockCycleTime

   Mem-stall cycles = Instructions/program x Misses/instruction x Miss penalty
}}} 

'''Ignoring memory system behavior in writing programs or in general code in a compiler'''

IMPORTANT TO UNDERSTAND

'''Extending an address space by adding segments on top of an unsegmented address space.'''

If you outgrow your address space, better to replace it by a new larger address space (We went fro 16 --> 32 bit addresses). Now we are facing this problem again and we are going from 32 --> 64 bit addressing. Why not segment? Because the programmer must then deal with the issue, not the hardware - this makes for very difficult programming and usually results in low performance.

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